- class PadDelay(fill_very_end=True)¶
Padding idle time with Delay instructions.
Consecutive delays will be merged in the output of this pass.
The ASAP-scheduled circuit output may become
┌────────────────┐ q_0: ┤ Delay(160[dt]) ├──■── └─────┬───┬──────┘┌─┴─┐ q_1: ──────┤ X ├───────┤ X ├ └───┘ └───┘
Note that the additional idle time of 60dt on the
q_0wire coming from the duration difference between
Delayof 100dt (
XGateof 160 dt (
q_1) is absorbed in the delay instruction on the
q_0wire, i.e. in total 160 dt.
BasePaddingpass for details.
Create new padding delay pass.
bool) – Set
Trueto fill the end of circuit with delay.
Return the name of the pass.
Run the padding pass on
Check if the pass is an analysis pass.
If the pass is an AnalysisPass, that means that the pass can analyze the DAG and write the results of that analysis in the property set. Modifications on the DAG are not allowed by this kind of pass.
Check if the pass is a transformation pass.
If the pass is a TransformationPass, that means that the pass can manipulate the DAG, but cannot modify the property set (but it can be read).